The present invention relates generally to non-volatile memory cells and in particular the present invention relates to flash memory cells.
Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicate a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write.
Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. The transistors can be erased to restore the threshold voltage of the transistor. The memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. These non-volatile memory devices are commonly referred to as flash memories.
The non-volatile memory cells are fabricated as floating gate memory cells and include a source region and a drain region that is laterally spaced apart from the source region to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and is can also made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is xe2x80x9cfloatingxe2x80x9d in dielectric so that it is insulated from both the channel and the control gate.
As semiconductor devices get smaller in size, designers are faced with problems associated with the production of memory cells that consume a small enough amount of surface area to meet design criteria, yet maintain sufficient performance in spite of this smaller size.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved non-volatile memory cell.
The above-mentioned problems with non-volatile memory cells and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a pair of floating gate transistors comprises a pillar of silicon vertically extending from a substrate, an implanted drain region located in a top region of the pillar; and a pair of source regions implanted in the substrate. The pair of source regions are located on opposite sides of the pillar. First and second floating gates are located on opposite sides of the pillar and insulated from the pillar by gate oxide. First and second control gates are located on opposite sides of the pillar and insulated from the first and second floating gates.
In another embodiment, a non-volatile memory array comprises a pillar of silicon vertically extending from a substrate, an implanted drain region located in a top region of the pillar; and a pair of source regions implanted in the substrate. The pair of source regions are located on opposite sides of the pillar. First and second floating gates are located on opposite sides of the pillar and insulated from the pillar by gate oxide. First and second control gates are located on opposite sides of the pillar and insulated from the first and second floating gates. The first and second control gates are fabricated as parallel polysilicon rails, and the pair of source regions are fabricated as parallel source implant rails generally extending under the first and second control gates. A drain contact vertically extends from the top region of the pillar, and first and second source contacts vertically extend from the pair of source regions. A source conductor is coupled to a top of the first and second source contacts. Finally, a drain conductor is coupled to a top of the drain contact. The source and drain conductors extend in a horizontal direction generally perpendicular to the control gates.
A method of fabricating non-volatile memory cells comprises forming a pillar of silicon vertically extending above a substrate, implanting a drain region in a top of the pillar, and implanting first and second source regions in the substrate and adjacent to the pillar. The first and second source regions are located on opposite sides of the pillar. The method further comprises depositing a gate oxide on at least vertical sides of the pillar facing the first and second source regions, forming floating gates adjacent to and on opposite sides of the pillar, and forming first and second control gates insulated from the floating gates and located on opposite sides of the pillar.